Frame memory circuit

ABSTRACT

A memory circuit ( 14 ) having features specifically adaptedto permit the memory circuit ( 14 ) to serve as a video frame memory is disclosed. The memory circuit ( 14 ) contains a dynamic random access memory array ( 24 ) with buffers ( 18, 20 ) on input and output data ports ( 22 ) thereof to permit asynchronious read, write and refresh accesses to the memory array ( 24 ). The memory circuit ( 14 ) is accessed both serially and randomly. An address generator ( 28 ) contains an address buffer register ( 36 ) which stores a random access address and an address sequencer ( 40 ) which provides a stream of addresses to the memory array ( 24 ). An initial address for the stream of addresses is the random access address stored in the address buffer register ( 36 ).

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates in general to digital memorycircuits. Specifically, the present invention relates to digital memorycircuits which have particular advantages when used in connection withvideo applications.

BACKGROUND OF THE INVENTION

[0002] Digital TV, VCR, and related video applications often utilize aframe or field memory that stores pixels which together represent anentire frame of video. Such a frame memory is used in producing avariety of special effects, such as frame freezing, zoom, pan, splitscreen monitoring, and the like. Although a frame memory may beconstructed using conventional discrete integrated circuits, such aframe memory is relatively expensive, dissipates an undesirably largeamount of power, and occupies an undesirably large amount of space. Whensuch a frame memory is targeted for use in a commercial product, theseproblems are major ones. Accordingly, a single integrated circuit,either alone or in combination with as few other integrated circuits aspossible, improves upon a frame memory which has been constructed fromconventional discrete integrated circuits.

[0003] Prior art integrated circuit devices have attempted to addressthe frame memory problem. However, such devices fail to provide anarchitecture which adequately addresses video application needs. Forexample, devices which include only a few of the typically needed framememory functions may be used in providing a wide variety of specialeffects. However, they must be combined with such a large quantity ofconventional discrete integrated circuits that little improvementresults over constructing a frame memory entirely from conventionaldiscrete integrated circuits. On the other hand, a conventional framememory integrated circuit may include a random access memory withcomplete on-chip address calculation. A video application which utilizessuch a frame memory accesses the entire frame memory serially. Thus,frame freeze and split screen monitoring special effects are supported.However, zoom and pan functions are either impossible or impracticalusing such a device.

[0004] Accordingly, the industry feels a need for a frame memoryintegrated circuit which optimizes circuit architecture to accommodate awide variety of special effects without requiring a large quantity ofsurrounding integrated circuits.

SUMMARY OF THE INVENTION

[0005] Accordingly, it is an advantage of the present invention that aframe memory circuit is provided which permits limited random access.Consequently, a device constructed according to the teachings of thepresent invention may be efficiently used to perform a wide variety ofspecial effect video applications.

[0006] Another advantage of the present invention is that a memorycircuit is provided which includes a variety of address calculationmodes. Thus, a portion of the address calculations for certain specialeffect functions may be transferred to the memory circuit, and a videoapplication which utilizes such a memory circuit need not allocateprocessing power to such calculations.

[0007] The above advantages of the present invention are carried out inone form by a memory circuit which stores and provides streams of data.This memory circuit supports both serial access and random access. Adata input of a random access memory array couples to a data buffer sothat the data buffer may synchronize operation of the memory array withthe streams of data. An address input of the random access memory arraycouples to an address sequencer which generates a sequence of memoryaddresses that are successively applied to the memory array. An addressbuffer register also couples to the address sequencer. The addressbuffer register supplies a random access address to the addresssequencer to initialize the sequence of memory addresses supplied by theaddress sequencer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the present invention may bederived by referring to the detailed description and claims whenconsidered in connection with the accompanying drawings, in which likereference numbers indicate like features throughout the drawings, andwherein:

[0009]FIG. 1 illustrates a frame of a video display screen with whichthe present invention may be used;

[0010]FIG. 2 shows a block diagram of a memory circuit built accordingto the teachings of the present invention;

[0011]FIG. 3 shows a block diagram of a first alternate embodiment of anaddress generator portion of a memory circuit built according to theteachings of the present invention;

[0012]FIG. 4 shows a block diagram of a second alternate embodiment ofan address generator portion of a memory circuit built according to theteachings of the present invention; and

[0013]FIG. 5 shows a block diagram of an address sequencer utilized bythe address generator portion of a memory circuit built according to theteachings of the present invention.

DETAILED DESCRIPTION

[0014]FIG. 1 illustrates a video frame 10, such as may appear on a TVtube or other video display terminal. Although frame 10 may appear as acontinuous video picture to a viewer, frame 10 may be electricallyrepresented as a multiplicity of digitized pixels 12. Each one of pixels12 defines parameters, such as color and relative intensity, for one ofa multiplicity of very small areas within the picture of frame 10.Accordingly, frame 10 may contain a relatively large number of pixels12. For example, a frame containing 488 columns of pixels 12 by 488 rowsof pixels 12 has a total of 238,144 pixels per frame.

[0015] Pixels 12 are typically transmitted or otherwise processed in apredetermined order to preserve the spatial relationships between pixels12. For example, in a conventional raster scan application, pixels 12may be transmitted to a memory device or a video display in successiveorder beginning with a pixel 12 a, that represents the pixel 12 in thefirst column of the first row of frame 10, and continuing in successiveorder to a pixel 12 b, which represents the pixel 12 in the last columnof the first row of frame 10. Immediately following the transmission ofpixel 12 b and sync information (not shown), a pixel 12 c, whichrepresents the pixel 12 in the first column of the second row, may betransmitted followed in successive order by the remaining pixels 12contained in the second row of frame 10. Transmission of pixels 12continues in this fashion until a pixel 12 d, which represents the pixel12 in the last column of the last row of frame 10, has been transmitted.Thus, any processing device which knows the timing relationship betweena pixel 12 and beginning pixel 12 a also knows or can easily calculatethe spatial location of such pixel 12 within frame 10.

[0016] A digital TV, VCR, or the like may contain a large frame or fieldmemory which is capable of storing all of pixels 12 within frame 10.Pixels 12 collectively appear as a serial data stream to the framememory. Except for special effects, the relative order of pixels 12 inthis serial data stream must generally be preserved when read from theframe memory to preserve the spatial relationships between pixels 12.However, various special effects do not require this preserved order,and valuable computation time may be wasted by precisely preserving theorder of pixels 12 as pixels 12 are being read from the frame memory.

[0017] One such special effect is a zoom effect wherein a small portionof a frame is expanded to fill an entire video display. For example, ifframe 10 in FIG. 1 represents an entire video display, then an areawithin frame 10 bounded by rows i and j and columns m and n is expandedin a zoom special effect to fill the entire frame 10. Thus, in the zoomspecial effect all of pixels 12 residing within frame 10 outside of thearea bounded by rows i and j and columns m and n are inactive and may bediscarded. In other words, these inactive ones of pixels 12 need not bestored or read from the frame memory. Consequently, the pixel 12 locatedat column m and row i will be utilized as first pixel 12 a in the zoomspecial effect. Active pixels 12 may be duplicated to complete an entirerow of frame 10, and rows may be duplicated to complete the verticalcomponent of the zoom effect.

[0018] In a split screen special effect, an entire frame 10 may beshrunk into a small area of a screen, such as that bounded by row j andthe last row of frame 10, and column n and the last column of frame 10.This special effect is accomplished by utilizing only one of pixels 12out of each of a predetermined number of pixels 12 from an entire frame10 of pixels 12, and ignoring the intervening inactive ones of pixels 12(i.e. skipping pixels). For the example depicted in FIG. 1, the shrunkenframe is formed using only pixels 12 from one of every three columns andone of every three rows of frame 10.

[0019] The present invention provides a memory circuit which series as aframe memory and permits these and other special effects to be performedefficiently. FIG. 2 shows a block diagram of a memory circuit 14 builtaccording to the teachings of the present invention. In general, thepreferred embodiment of memory circuit 14 represents a single chipintegrated circuit that contains 2²⁰ or 1,048,576 bits of memory storageorganized as 262,144 four bit wide words. Accordingly, a sufficientquantity of words are provided to buffer or store an entire 488×488frame of pixels 12 (see FIG. 1). If more than four bits of precision arerequired to accurately describe each pixel, then additional ones ofmemory circuit 14 may be used to store such additional bits.

[0020] Memory circuit 14 generally operates in a serial access mode buthas particular features which permit random access of memory circuit 14on a limited scale. Those skilled in the art will understand that serialaccess refers to a mode of storing and reading data in which data mustbe read out from a memory in the same order in which it was stored intothe memory. Furthermore, random access refers to the ability to write,read, or otherwise access any location in a memory array by suppiying aunique address which corresponds to such memory location.

[0021] Specifically, memory circuit 14 includes a serial pixel datainput 16 a, which in the preferred embodiment supplies four bits ofdata. Serial pixel data input 16 a couples to an input port of a writeserial latch 18 a, and an output port of write serial latch 18 a couplesto an input port of a write register 20 a. An output port of writeregister 20 a couples to a data input port 22 a of a memory array 24. inthe preferred embodiment, memory array 24 is a dynamic random accessmemory (DRAM) array containing 2¹⁸ or 262,144 four bit memory locations.A data output port 22 b of memory array 24 couples to a data input portof a read register 20 b, and a data output port of read register 20 bcouples to a data input port of a read serial latch 18 b. A data outputport of read serial latch 18 b couples to a serial pixel data output 16b, which in the preferred embodiment provides four bits of data.

[0022] A serial write clock terminal 26 a couples to a write addressgenerator 28 a, an arbitration and control circuit 30, and a clock inputof write serial latch 18 a. Similarly, a serial read clock terminal 26 bcouples to a read address generator 28 b, arbitration and controlcircuit 30, and a clock input of read serial latch 18 b. A refreshaddress and timing circuit 32 has an output which couples to an input ofarbitration and control circuit 30, and outputs from arbitration andcontrol circuit 30 couple to a clock input of write register 20 a, aclock input of read register 20 b, a control input of memory array 24,and an address input of memory array 24.

[0023] As shown in FIG. 2, address generators 28 a and 28 b arestructurally similar to one another in the preferred embodiment. thus, awrite control data terminal 34 a couples to a serial data input of anaddress buffer register 36 a in write address generator 28 a. A readcontrol data terminal 34 b couples to a serial data input of an addressbuffer register 36 b in read address generator 28 b. Likewise, a writecontrol strobe terminal 38 a couples to a clock input of address bufferregister 36 a, and a read control strobe terminal 38 b couples to aclock input of address buffer register 36 b. A data output of addressbuffer register 36 a couples to a data input of an address sequencer 40a, and a data output of address buffer register 36 b couples to a datainput of an address sequencer 40 b. A write reset terminal 42 a couplesto a clear input of address sequencer 40 a, and a write transferterminal 44 a couples to a preset input of address sequencer 40 a. Aread reset terminal 42 b couples to a clear input of address sequencer40 b, and a read transfer terminal 44 b couples to a preset input ofaddress sequencer 40 b. Terminal 26 a couples to a clock input ofaddress sequencer 40 a within address generator 28 a, and terminal 26 bcouples to a clock input of address sequencer 40 b within addressgenerator 28 b. An output 46 a of address sequencer 40 a presents theoutput signal from address generator 28 a and couples to an input ofarbitration and control circuit 30. Likewise, an output 46 b of addresssequencer 40 b presents the output signal from address generator 20 band couples to arbitration and control circuit 30. Memory circuit 14 maybe provided in a 20 pin integrated circuit package.

[0024] As discussed above, memory circuit 14 may be operated in either aserial or a limited random access mode. In addition, the storing orwriting of data into memory circuit 14 may occur asynchroniously withthe reading or providing of data from memory circuit 14. Memory circuit14 may be written into serially by activating write reset signal onterminal 42 a to clear address sequencer 40 a. Then, a four bit widestream of serial data may be stored in memory circuit 14 by applying thefour bit data nibbles at data input 16 a while asserting a serial writeclock signal at terminal 26 a. One assertion of the serial write clocksignal causes write serial latch 18 a to temporarily store or buffer onefour bit data nibble. Write serial latch 18 a operates as a four bitwide shift register. Thus, subsequent four bit nibbles from the datastream of serial pixel data applied at data input 16 a are shifted intoserial latch 18 a upon subsequent assertions of the serial write clocksignal.

[0025] In addition, each assertion of the serial write clock signalcauses address sequencer 40 a of write address generator 28 a to supplya new a random access address to arbitration and control circuit 30. Inother words, address sequencer 40 a provides a stream of addresses toarbitration and control circuit 30 which corresponds to the stream ofdata being stored in write serial latch 18 a.

[0026] Arbitration and control circuit 30 receives addresses fromaddress generators 28 a-28 b and refresh address and timing circuit 32.Circuit 30 monitors these inputs and various timing signals to decidewhich of the addresses provided on these inputs should be transferred tomemory array 24. Arbitration and control circuit 30 includesconventional logic circuits for controlling the timing operation of thedynamic memories which comprise memory array 24. Thus, arbitration andcontrol circuit 30 passes an address generated by address generator 28 aonto memory array 24 so that data may be written into memory array 24,but a delay may occur due to refresh operations or read accesses ofmemory array 24. Accordingly, arbitration and control circuit 30 mayadditionally contain storage devices so that addresses generated byaddress generators 28 a-28 b are not lost when immediate access tomemory array 24 is blocked. When arbitration and control circuit 30identifies a time at which the serial pixel data may be written intomemory array 24, such data is transferred from write serial latch 18 ainto write register 20 a and then written into memory array 24.Accordingly, write serial latch 18 a and write register 20 a togetherrepresent a double buffering scheme which permits asynchroniousoperation of memory array 24 with the storing of serial pixel data intomemory circuit 14.

[0027] The reading of data from memory array 24 occurs in a mannersimilar to that described above for the storing of data into memoryarray 24. Thus, an address generated by address generator 28 b istransferred through arbitration and control circuit 30 at an appropriatetime to cause data from memory array 24 to be read into read register 20b. Thereafter, this data is transferred into read serial latch 18 b sothat such data may be provided at data output terminal 16 b through theapplication of a serial read clock signal at terminal 26 b. Serial datais provided at output 16 b asynchroniously with the operation of memoryarray 24 and asynchroniously with the storing of serial pixel data intomemory circuit 14 at terminal 16 a.

[0028] The limited random access feature of memory circuit 14 isprovided through address generators 28 a-28 b. In the embodiment ofmemory circuit 14 shown in FIG. 2, write address generator 28 a and readaddress generator 28 b are structurally and operationally identical,except that write address generator 28 a provides write addresses whileread address generator 28 b provides read addresses. Accordingly, bothof address generators 28 a-28 b are described below by reference only towrite address generator 28 a. Those skilled in the art will recognizethat read address generator 28 b operates identically in the preferredembodiment.

[0029] A random access address may be serially loaded into addressbuffer register 36 a by applying such address to control data terminal34 a in a sequential manner and activating a control strobe signalapplied at terminal 38 a when valid data appear at terminal 34 a. Thus,in the embodiment shown in FIG. 2, address buffer register 36 arepresents a serial shift register. The use of a serial shift registerconserves the number of external pins needed for constructing memorycircuit 14 in an integrated circuit when compared to a parallel loadedregister. After the random access address has been entered into addressbuffer register 36 a, it may be transferred to data sequencer 40 a bythe application of a write transfer signal at terminal 44 a. In thepreferred embodiments of the present invention, address sequencer 40 amay represent a presetable, binary counter or other presetablesequencing circuit. Thus, the transferred address initiates a sequenceof addresses which are subsequently generated by address generator 28 a.If address sequencer 40 a represents a binary counter, then subsequentaddresses will increment or decrement starting with this preset value.

[0030] If memory array 24 contains 2 four bit words of memory, thenaddress buffer register 36 a may advantageously represent an 18 bitregister, and address sequencer 40 a may represent an 18 bit counter, orother sequencing circuit. On the other hand, address buffer register 36a and address sequencer 40 a may contain fever bits, such as nine bitsfor example. In the nine bit situation, the random access addressprovided by address buffer register 36 a could access the beginning ofmemory pages or rows wherein each page or row contains 2⁹ or 512 wordsof memory.

[0031] The inclusion of address buffer register 36 a to provide alimited random access feature permits memory circuit 14 to beefficiently utilized in a zoom special effect. For example, a zoomeffect may be accomplished by writing an entire frame of memory intomemory array 24 using a serial access mode. A beginning pixel address,such as the address of a pixel located at row i column m, in FIG. 1, maythen be loaded into read address buffer register 36 b and transferred toaddress sequencer 40 b. A first row, such as row i, of the portion offrame 10 which is to be expanded into an entire frame may then be readfrom memory array 24 in a serial or sequential mode until a pixelcorresponding to, for example, row i, column n appears at outputterminal 16 b. A row may be repeated as often as necessary to achievevertical zoom by transferring the random access address from addressbuffer register 36 b to address sequencer 40 b. An address correspondingto the pixel located at row i+1 and column m may then be loaded intoaddress buffer register 36 b and transferred to address sequencer 40 b.This process continues until a final pixel for the frame to be expandedhas been output from memory array 24. Due to this feature, a videosystem need not start accesses of memory circuit 12 at an initialaddress, such as pixel 12 a (shown in FIG. 1) and access inactive pixelsstored within memory array 24. Faster operation results.

[0032] The present invention contemplates alternate embodiments ofaddress generators 28 a-28 b. A first alternate embodiment of addressgenerators 28 a-28 b is shown in FIG. 3. FIG. 3 shows only one ofaddress generators 28. The address generator 28 shown in FIG. 3 mayserve as either write address generator 28 a or read address generator28 b (see FIG. 2).

[0033] In this first alternate embodiment of an address generator 28,address buffer register 36 may be loaded both serially and in parallel.Thus, control data terminal 34, which may represent either write controldata terminal 34 a or read control data termin,al 34 b, as discussedabove in connection with FIG. 2, couples to the serial data input ofaddress buffer register 36. Control strobe terminal 38 couples to theserial clock input of address buffer register 36 and a serial clockinput of an address offset register 48. The parallel data output ofaddress buffer register 36 couples to a first input of an adder 50 andthe data input of address sequencer 40. A parallel data output ofaddress offset register 46 couples to a second input of adder 50. Anoutput of adder 50 couples to a parallel data input of address bufferregister 36, and transfer terminal 44 couples to a parallel clock inputof address buffer 36 and the preset input of address sequencer 40. Amost significant bit from the parallel data output or a serial outputbit, of address buffer register 36 couples to a serial data input ofaddress offset register 48. Serial clock terminal 26 couples to theclock input of address sequencer 40, and reset terminal 42 couples to aclear input of address sequencer 40. A data output of address sequencer40 couples to address generator output 46.

[0034] Address buffer register 36 and address sequencer 40 operate inthis first alternate embodiment similarly to their above-describedoperation in connection with address generator 28 a-28 b of FIG. 2.However, in this first alternate embodiment, the control data providedat terminal 34 is used to load both address buffer register 36 andaddress offset register 48. Thus, additional bits of control data areloaded into memory circuit 14 without requiring additional integratedcircuit pins. Moreover, a most significant bit, or a serial output bit51, from address offset register 48 may advantageously be routed to thecontrol data input for the other one of read and write addressgenerators 28 a and 28 b (see FIG. 1). In addition, the control strobesignal applied at terminal 38 may be routed to the other one of controlstrobe terminals 38 a and 38 b of FIG. 2. These two connections betweenaddress generators 28 a and 28 b eliminate two integrated circuit pinsfrom the structure shown in FIG. 2.

[0035] In this first alternate embodiment of the present invention, thecontrol data contained in address offset register 48 is added to acurrent initial address value contained in address buffer register 36 toprovide a new initializing random access address value. This newinitializing value is loaded into address buffer register 36 when thecurrent address value is transferred into address sequencer 40.

[0036] Referring additionally to FIG. 1, the first alternate embodimentof the present invention may be advantageous in performing, for example,the zoom special effect. Thus, the address offset value loaded intoaddress offset register 48 may represent the quantity of inactive pixelsoccurring between column n of one row and column m of the next row. Atthe end of each frame row a transfer signal may be asserted on terminal44, and the random access address of the next active pixel,corresponding to column n of the next row, is automatically calculatedand stored in address buffer register 36 to initiate another sequence ofsequential accesses to memory circuit 16. Complexity of a video systememploying memory circuit 14 decreases because components external tomemory circuit 14 need not calculate this address.

[0037] A second alternate embodiment of address generators 28 a-28 bfrom FIG. 2 is shown in FIG. 4. The FIG. 4 embodiment illustrates thatrandom access addresses may be loaded into address buffer register 36 ina parallel fashion, which may be more compatible with conventionalmicroprocessor integrated circuits. However, the number of integratedcircuit pins needed to implement this embodiment increases over theembodiments discussed above in connection with FIGS. 2 and 3. Inaddition, FIG. 4 shows the inclusion of an alternate address bufferregister 52 in addition to address buffer register 36. Specifically,control data terminals 34 may advantageously provide an eight bitmicroprocessor data bus which couples to data inputs of individual eightbit portions 54 a, 54 b, and 54 c of address buffer register 36. Inaddition, control data terminals 34 couple to data inputs of individualeight bit portions 56 a, 56 b, and 56 c of alternate address bufferregister 52. Data outputs of individual portions 54 a-54 c together forma 24 bit bus which couples to a first data input of a multiplexer 58.Likewise, data outputs of individual portions 56 a-56 c form a 24 bitbus which couples to a second data input of multiplexer 58. A dataoutput of multiplexer 58 couples to a data input of a binary counterwhich serves as address sequencer 40 in this second alternateembodiment. Of course, those skilled in the art will recognize that thenumber of subregisters included within address buffer register 36 andalternate address buffer register 52 and the number of bits containedwithin the buses described above are subject to a substantial variationin accordance with specific application requirements.

[0038] In addition, microprocessor address input terminals 60 a, 60 b,and 60 c, couple to address inputs of a decoder 62 and an address inputterminal 60 d couples to an enable input of decoder 62. The controlstrobe terminal 38, discussed above, couples to an enable input ofdecoder 62. Outputs O1-O6 of decoder 62 couple to clock inputs ofindividual address buffer register portions 54 a-54 c and clock inputsof individual alternate address buffer register portions 56 a-56 c,respectively. An output 07 from decoder 62 couples to a clock input of aflip flop 64 which is configured to toggle upon the activation of theclock input. An output of flip flop 64 couples to a select input ofmultiplexer 58. An output O8 of decoder 62 couples to a preset input ofbinary counter 40. The serial clock 26 couples to a clock input ofbinary counter 40, and reset terminal 42 couples to a clear input offlip flop 64 and a clear input of binary counter 40. An output of binarycounter 40 couples to output 46 of address generator 28.

[0039] In this second alternate embodiment of address generator 28, oneinitializing random access address may be stored in address register 36while an alternate initializing random access address is stored inalternate address buffer register 52. A microprocessor (not shown) maystore these addresses in memory circuit 14 through conventional memoryor I/O write operations to addresses specified by signals applied onterminals 60 a-60 c. An address input bit applied at terminal 60 d mayadvantageously distinguish between a write address generator 28 a and aread address generator 28 b (see FIG. 1). By applying an active signalto reset terminal 42; flip flop 64 and binary counter 40 may beinitialized to a cleared state. At this point, address generator 28operates substantially as described above in connection with FIG. 2.However, an alternate random access address stored in alternate addressbuffer 52 may selectively preset binary counter 40. A microprocessorwrite operation which toggles flip flop 54, followed by a microprocessorwrite operation that transfers data into binary counter 40, presetsbinary counter 40 with an alternate random access address. Flip flop 64may be toggled by performing a write operation to the address whichactivates output O7 of decoder 62. A transfer operation from theselected one of address buffer registers 36 and 52 occurs by writing tothe address which activates the output O8 of decoder 62.

[0040] Alternate address buffer register 52 may advantageously be usedby a video system to efficiently buffer a line within a frame of data.Since memory circuit 14 of the preferred embodiment contains asufficient quantity of memory to accommodate 2¹⁸ or 262,144 pixels,memory circuit 14 has unused memory locations when used to store asingle frame of data which contains, for example, 480 pixel columns by480 pixel rows. Accordingly, a random access address in this unusedportion of memory may be loaded in alternate address buffer register 52.A single line of a frame may be efficiently stored in memory circuit 14by transferring this alternate address value to binary counter 40, thensequentially storing such line of pixels into the otherwise unusedportion of memory circuit 14.

[0041] In addition, the present invention contemplates alternativeembodiments for address sequencer 40. As shown in FIG. 4, addresssequencer 40 may represent a conventional presetable, clearable, binarycounter. Such circuits are well known to those skilled in the art andneed not be described in detail herein. However, address sequencer 40may alternatively represent a circuit which increments or decrements bya variable step value which may differ from the value of one. Such acircuit is shown in FIG. 5.

[0042] Accordingly, in FIG. 5 the address sequencer data input couplesto a first input of a multiplexer 66, the address sequencer's presetterminal couples to a select input of multiplexer 66. An output ofmultiplexer 66 couples to a data input of a register 68, and the clockinput of address sequencer 40 couples to a clock input of register 68.Likewise, the reset terminal 42 couples to a clear input of register 68.A data output of register 68 provides the data output of addresssequencer 40 and additionally couples to a first input of an adder 70.An output of adder 70 couples to a second input of multiplexer 66. Thecontrol data terminals 34, discussed above in connection with FIGS. 2-4,couple to a data input of a register 72. Additionally, the controlstrobe terminal 38, discussed above in connection with FIGS. 2-4,couples to a clock input of register 72. A data output of register 72couples to a second input of adder 70.

[0043] In this FIG. 5 embodiment of address sequencer 40, register 72may represent either a parallel or a serially loaded register, asdiscussed above in connection with FIGS. 2-4. Additionally, if register72 represents a serially loaded register, then register 72 may representone register out of many coupled together in a long chain of seriallyloaded registers, as discussed above in connection with FIG. 3. The dataloaded into register 72 is intended to represent a increment step bywhich address sequencer 40 generates successive addresses at output 46of address generator 28. A current output of address sequencer 40 isadded to this step increment value in adder 70, and routed throughmultiplexer 66 back to register 68. Thus, a subsequent address generatedby address sequencer 40 equals the previous address plus the addressstep increment contained in register 72. This address step incrementneed not equal the value of one but may equal any positive or negativevalue. Furthermore, if the number of bits contained in the buses whichcouple register 72, adder 70, multiplexer 66, and register 68 togetheris greater than the number of bits provided at the output of addresssequencer 40, then subsequent addresses may be incremented in fractionalsteps.

[0044] Address sequencer 40 may be preset, or initialized, with a randomaccess address by applying an active signal on the preset terminal,supplying data at the data input terminals, and clocking the clocksignal of address sequencer 40. Thus, this initializing random accessvalue is loaded directly into register 68. In addition, addresssequencer 40 may be cleared, or reset, by applying a reset signal to theclear input terminal.

[0045] Referring additionally to FIG. 1, the address sequencer 40depicted in FIG. 5 is useful in performing the split screen specialeffect where an entire frame is displayed in only a small portion of avideo screen, such as the lower right hand portion shown in FIG. 1. Withthis special effect, if memory circuit 14 has every pixel 12 of a frame10 stored therein, then only one out of every group of a predeterminednumber of stored pixels is active in constructing the shrunken screen.Address sequencer 40 shown in FIG. 5 allows memory circuit 14 to provideonly the active pixels by supplying a sequence of addresses which omitsinactive pixel addresses.

[0046] In summary, the present invention provides a memory circuit whichallows a video system to efficiently perform special effects.Specifically, the inclusion of various limited random accessing featuresallows memory circuit 14 to store and/or provide only active pixels fora given special effect and not inactive pixels.

[0047] Consequently, active pixels may be retrieved from memory circuit14 much quicker than occurs with the use of prior art frame memorycircuits.

[0048] The foregoing description uses preferred embodiments toillustrate the present invention. However, those skilled in the art willrecognize that changes and modifications may be made in theseembodiments without departing from the scope of the present invention.For example, read address generator 28 b need not precisely resemblewrite address generator 28 a. Additionally, although the embodimentsdepicted in FIGS. 3-5 are mentioned above as being alternativeembodiments, nothing prevents one skilled in the art from combining theteachings from more than one of these alternate embodiments into asingle frame memory circuit 14. Moreover, those skilled in the art willrecognize that additional address processing cap abilities may be builtinto frame memory circuit 14. Such additional address processingcapabilities may include the addition of a signal which indicates theend of a frame line, a signal which indicates the end of a frame, andthe automatic transferring of random access addresses to an addresssequencer upon the occurrence of the end of line and end of framesignals. Furthermore, although specific frame and memory arraydimensions have been presented herein to aid in teaching the presentinvention, it is intended that the present invention not be limited toany particular dimensions. These and other modifications obvious tothose skilled in the art are intended to be included within the scope ofthe present invention.

What is claimed is:
 1. A memory circuit for storing and providingstreams of data, said memory circuit accommodating both serial accessand random access, and said memory circuit comprising: a random accessmemory array having an address input and a data port; a data bufferhaving a data port coupled to said memory array data port, said databuffer synchronizing operation of said memory array to the streams ofdata; an address sequencer having a data input and having an outputcoupled to said memory array address input, said address sequencergenerating a sequence of memory addresses to be successively applied tosaid memory array; and an address buffer register having an outputcoupled to said address sequencer data input, said address bufferregister supplying a random access address that initializes the sequenceof memory addresses generated by said address sequencer.
 2. A memorycircuit as claimed in claim 1 wherein said address buffer registercomprises a serially loaded shift register.
 3. A memory circuit asclaimed in claim 1 additionally comprising a terminal coupled to saidaddress sequencer and adapted to receive a signal which causes datacontained in said address buffer register to transfer to said addresssequencer.
 4. A memory circuit as claimed in claim 1 wherein said memoryarray, data buffer, address sequencer, and address buffer register areincluded within a single integrated circuit.
 5. A memory circuit asclaimed in claim 1 wherein said address sequencer comprises a binarycounter having a data input coupled to the output of said address bufferregister and an output coupled to the address input of said memoryarray.
 6. A memory circuit as claimed in claim 1 wherein said addresssequencer comprises: a first register having a data input coupled to anode which serves as said address sequencer data input and an outputwhich serves as said address sequencer output; a second register havingan output, said second register being for storing an increment stepvalue; and an adder having a first input coupled said first registeroutput, a second input coupled to said second register output, and anoutput coupled to said first register data input.
 7. A memory circuit asclaimed in claim 1 wherein said data buffer synchronizes operation ofsaid memory array to the data stream being stored into said memoryarray, said address sequencer generates memory addresses at which thestored data stream is written into said memory array, and said memorycircuit additionally comprises: a second data buffer having a data portcoupled to said memory array data port, said second data buffer beingfor synchronizing operation of said memory array to the data streamprovided by said memory circuit; a second address sequencer having anoutput coupled to said memory array address input and a data input, saidsecond address sequencer generating a sequence of memory addresses to beapplied to said memory array for reading the provided data stream fromsaid memory array; and a second address buffer register having an outputcoupled to said second address generator data input, said second addressbuffer register supplying a random access address that initializes thesequence of memory addresses generated by said second address sequencer.8. A memory circuit as claimed in claim 1 additionally comprising: anaddress offset register having an output, said address offset registerbeing for storing address offset data; and an adder having a first inputcoupled to said address buffer register output, a second input coupledto said address offset register output, and an output coupled to a datainput of said address buffer register, said adder providing a randomaccess address representing a sum of a past random access address andsaid address offset data.
 9. A memory circuit as claimed in claim 1additionally comprising an alternate address buffer register having anoutput coupled to said address sequencer data input, said alternateaddress buffer register supplying an alternate random access addressthat initializes an alternate sequence of memory addresses generated bysaid address sequencer.
 10. An integrated memory circuit for storing andproviding streams of data, said integrated memory circuit accommodatingserial access and limited random access, and said integrated memorycircuit comprising: a random access memory array having an addressinput, a data input port, and a data output port; a first data bufferhaving a data port coupled to said memory array data input port, saidfirst data buffer synchronizing operation of said memory array to thestored stream of data; a second data buffer having a data port coupledto said memory array data output port, said second data buffersynchronizing operation of said memory array to the provided stream ofdata; and first and second address generators wherein said first addressgenerator generates addresses used for writing the stored data streaminto said memory array, said second address generator generatesaddresses used for reading the provided data stream from said memoryarray, and each of said first and second address generators comprises: abinary counter having an output coupled to said memory array addressinput and a data input, said binary counter being for counting memoryaddresses to be applied to said memory array; and a serially loadedaddress buffer register having an output coupled to said binary counterdata input, said address buffer register being for supplying an initialrandom access memory address which starts the count of said binarycounter.
 11. A memory circuit as claimed in claim 10 wherein each ofsaid first and second address generators additionally comprises: anaddress offset register having an output, said address offset registerstoring address offset data; and an adder having a first input coupledto said address buffer register output, a second input coupled to saidaddress of set register output, and an output coupled to a data input ofsaid address buffer register, said adder providing a sum of a pastrandom access address and said address offset data to said addressbuffer register.
 12. A memory circuit as claimed in claim 10 whereineach of said first and second address generators additionally compr-sesan alternate buffer register having an output coupled to said binarycounter data input, said alternate address buffer register supplying analternate initial random access memory address which is counted by saidbinary counter.
 13. A method of storing and providing streams of datausing a random access memory array, said method comprising the steps of:buffering the streams of data into and out from the memory array so thatthe stored and provided data streams occurs asynchroniously withoperation of the memory array; generating a random access address; andgenerating a sequence of addresses initialized with said random accessaddress said addresses being successively applied to the random accessmemory array.
 14. A method as claimed in claim 13 wheren said generatinga random access address step comprises the step of serially loading aregister with the random access address.
 15. A method as claimed inclaim 13 wherein said generating a sequence step comprises the step ofcounting successive data items within the streams of data to generateaddresses for successive application to the random access memory array.16. A method as claimed in claim 13 wherein said generating a sequencestep generates addresses for writing the stored data stream into thearray, and said method additionally comprises the step of: generating asecond sequence of addresses which are successively applied to therandom access memory array for reading the provided data stream from thememory array; and supplying, to said generating a second sequence step,a random access address which initiates the successively appliedsequence of addresses.
 17. A method as claimed in claim 13 additionalcomprising the steps of: providing an address offset value; and addingthe address offset value to the random access address to generate asecond random access address.
 18. A method as claimed in claim 13additionally comprising the step of supplying, to said generating asequence step, a second random access address which initiates a secondsuccessively applied sequence of addresses.
 19. A method as claimed inclaim 13 wherein said generating a sequence step comprises the steps of:providing an increment step value; and adding the increment step valueto a current address from the sequenca of addresses to produce a nextaddress in the sequence of addresses.